표 2. | Table 2. 성능 요약 및 위상천이기 비교표 | Performance summary and comparison of phase shifters.

Ref	Process	Freq. (GHz)	Gain (dB)	Gain control topology	Calibration	RMS ϴerror (°)	PDC (mW)	Core area (mm2)
[3]	65 nm CMOS	30~32.5	−2.8	Multi-vector summation	No	2.6*/3.51)	18	0.21
[8]	45 nm SOI	27~33	−5.8	Polar vector modulator	Yes	0.8*	25	0.27
[9]	130 nm CMOS	26.55~29.4	−5	Polar vector modulator	Yes	2.33)*	27	0.284
[10]	180 nm CMOS	27~33	−5.17	N.A.	No	<42)	6.6	0.2423)
[11]	150 nm GAN HEMT	26.5~29.5	−8.45	N.A.	No	<4.54	0	3.45
This work	65 nm CMOS	29~33	−4.08	Multi-vector summation	No	1.711)	15	0.259

Total RMS phase error, ^*by only control.
External gate voltage control, based on measurement result.
Graphical analysis.