표 4. | Table 4. 다른 문헌 연구결과와 비교 | Comparison of this work with other digital phase noise measurements.

Items	[4]	[6]	[19]	This work
ADC bits	14	14~15	16	10
Bandwidth (MHz)	NA	1~30	80±7.5*1	8,000
HW implementation	ADC, FPGA	ADC, FPGA	Data capture	Data capture
Sampling clock implementation	External source	?	OCXO	Internal clock
fs (MHz)	65	75~105	100	~20 GHz*2
Sampling clock PN compensation	No	Yes	No	Yes
PN floor (dBc/Hz)	−125	−173	−155	−160*3

BandPass filter of 15 MHz bandwidth is employed.
MSO804A maximum sampling frequency.
f_s=10 GHz, M=10,000.감사의 글